In current DRAM, for gapless read/write, a single-cycle command pulse would be generated and propagate through the DRAM. However, since the command pulse is single-cycle wide, the command logic of the DRAM would run continuously for gapless access and the power consumption of the DRAM would be extremely high.
Therefore, in order to reducing the power consumption of the DRAM, area saving and ensure outputs and termination are enabled correctly, a circuit for command generation and clock control in DRAM devices and method thereof is necessary.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.